SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories

Variability in transistor performance will continue to increase with the scaling of technology. Transistors are more and more unreliable. Also, the noise-tolerant capability of circuits is less and less robust. To avoid the loss of yield and fault coverage, the design-for-testability circuit must be designed to be noise-tolerant. This paper presents a soft-error tolerant built-in self-test (SETBIST) design for random access memories (RAMs). Some soft-error-mitigation (SEM) techniques are proposed to enhance the softerror immunity of the instruction register, March operation generator, address generator, and data background generator. Experimental results show that the area overhead of the SETBIST is only about 1.1% for an 8K × 64-bit SRAM. Analysis results show that the SETBIST can effectively tolerate soft errors. We also use FPGA demonstration board to verify the SETBIST scheme.